An analog/digital converter is an integrated circuit that converts analog continuous signals to discrete digital numbers. Such converters are used in many electronic and communication applications in which signals must be converted from the analog to digital domain, such as for processing or transmission. A digital/analog converter (DAC) is used to perform the reverse operation. In an A/D converter, or ADC, an analog input is typically converted to a digital output according to a coding scheme.
One common way of implementing an electronic ADC is a pipeline ADC, which uses two or more steps. A coarse conversion is done in a first step. In a second step, a difference between the input signal and the coarse output is determined, for example using a DAC. This difference, or analog residue, is then converted finer, and the results are combined in a last step. This type of ADC is fast, has a high resolution and only requires a small die size.
An architecture of a pipeline A/D converter with N stages can be represented as in FIG. 1. The analog input is processed in the analog domain as follows:
1. Stage 1 quantizes its input (Ain) and creates a digital output (D1).
2. Stage 1 calculates an Analog Residue (AR1) by subtracting D1 times a reference voltage from the input signal (Ain) and multiplying the result by a gain A1:AR1=A1·(Ain−D1·Vref)3. Stage 2 quantizes the Analog Residue from stage 1 (AR1) and creates a digital output (D2).4. Stage 2 calculates an Analog Residue (AR2) by subtracting D2 times a reference voltage from its input signal (AR1) and multiplying the result by a given power of 2.AR2=A2·(AR1−D2·Vref)5. The last two steps are repeated for all the remaining stages from 3 to N.
Once digital outputs of all the stages are available, they are combined together as follows:
1. The output of stage N (DN) is multiplied by the weight of stage N (2^nN) to calculate the Digital Residue of Stage N−1 (DRN-1). Typically the weight of the last stage (N) is 1.DRN-1=2^nN·DN 2. The output of stage N−1 (DN-1) is multiplied by the weight of stage N−1 (2^nN-1) and added to the Digital Residue of Stage N−1 (DRN-1) to calculate the Digital Residue of Stage N−2 (DRN-2).DRN-2=2^nN-1·DN-1+DRN-1 3. The last step is repeated for all the stages from N−2 to 1 until the last operation is:Dout=2^n1·D1+DR1 
The final result can be expressed in the common form:
  Dout  =            ∑              j        =        1            N        ⁢                  2        ^                  n          j                    ·              D        j            
For the following discussion, it is useful to conceptually represent the pipeline A/D converter as a first stage followed by a back-end ADC composed of all the following stages, as in FIG. 2. To understand the limitations of the pipeline A/D converter, we need to look at the transfer characteristics of a stage. We will be referring to stage 1 as this is the most important for the pipeline in terms of performance, however all other stages will have similar characteristics. Since stage 1 has two outputs, one digital (D1 in FIG. 2) and one analog (AR1 in FIG. 2), there are two transfer characteristics, as shown in FIG. 3 for a typical implementation (the so-called 1.5 bit stage).
The transfer characteristic for AR1 is not readily observable in an A/D converter. Hence it is more useful to draw the transfer characteristics of D1 and DR1 instead of D1 and AR1. As previously mentioned, the digital output of the A/D converter is calculated from the sum of DR1 and D1 times the weight of stage 1. One can easily see that if we perform this operation on the D1 and DR1 transfer characteristics in FIG. 4, the resulting transfer characteristic is the expected linear transfer characteristic of an A/D converter.
Pipeline A/D converters suffer from limited gain in the amplifiers as well as from mismatches in analog components. These cause discontinuities in the transfer characteristic of the pipeline stage as in FIG. 5 and FIG. 6. Limited gain can be alleviated by designing very high-gain amplifiers (in excess of 90 dB), which is a challenge in itself, especially when large dynamic range and high-speed operation are required at the same time. Mismatches can be reduced only by increasing the area and power of the converter, which is a very expensive option. In order to reduce the effect of mismatches by a factor of 2, one needs to increase the area and power by a factor of 4, which becomes impractical when high resolution and high speed are required at the same time.
A conventional approach is to allow these errors (both low gain in the amplifiers as well as mismatches in the design) in the analog circuitry, but to calibrate the A/D converter, i.e. to compensate for them in either the analog domain or the digital domain. This is achieved by eliminating the discontinuities in the transfer characteristics. There are several known methods that perform calibration of the A/D converter in the background. Most of these methods require some specific modifications to the analog circuitry to allow for a given calibration method. In many cases such modifications are substantial.
Some background calibration techniques such as the one presented in U.S. Pat. No. 6,822,601 “Background-Calibrating Pipelined Analog-to-Digital Converter” to Silicon Integrated Systems Corp., require applying calibration signals, which need to be digitally filtered out from the ADC output.
Other background calibration techniques such as the one presented in U.S. Pat. No. 6,496,125 “A/D conversion” to Telefonaktiebolaget L M Ericsson require an auxiliary A/D converter. The A/D conversion is switched temporarily from the main A/D converter to the auxiliary A/D converter during short time intervals used for calibration of the first A/D converter.
Other background calibration techniques such as the one presented in U.S. Pat. No. 6,473,012 “A/D converter background calibration” to Telefonaktiebolaget L M Ericsson require random time interval generators that initiate background calibration at randomly selected time instants. The missing samples need to be filled by other means.
Other background calibration techniques such as the one presented in U.S. Pat. No. 6,784,824 “Analog-to-digital converter which is substantially independent of capacitor mismatch”, to Xilinx, Inc., use analog cancellation and require sampling the input signal twice.
Finally, the method presented in “Characterization and Digital Correction of Multi-Stage Analog-to-Digital Converters”, Dragos Cartina, 1997, M. Eng. Thesis, Carleton University, Ottawa, does not require any specific analog changes but implements the calibration completely in the digital domain, and will be described in further detail later.
Each of U.S. Pat. Nos. 6,822,601; 6,496,125; 6,473,012; 6,784,824; as well as the Cartina publication “Characterization and Digital Correction of Multi-Stage Analog-to-Digital Converters” describe related art and each is incorporated herein by reference.
The Cartina method, which will be further described in relation to FIGS. 7-9, does not require any specific analog circuitry just for calibration purposes. For calibration purposes one needs to measure the discontinuities in the transfer characteristics (B0-B1 and B2-B3 in FIG. 7). In practice one does not have access to the digital transfer characteristics, so one cannot use them to estimate their discontinuities and correct for them. However, one can have access to the histograms of the codes at the output of the A/D converter or at various points within the converter. If one needs to calibrate stage 1, the histograms of interest are those of DR1 for each D1 value. A calibration method is based on estimating the edges of the histograms, which in this case are B0, B1, B2, and B3, as shown in FIG. 8. The x-axis of the histograms in FIG. 8 represents codes such as −1000 or 0 or +1000, while the y-axis represents the number of times a particular code occurs. For instance, in the top histogram in FIG. 8, code −1000 happens more than 80 times (the plot is clipped at 80), code 0 happens about 50 times, and code +1000 never happens. The bound B0 is the edge of the histogram for the digital output code D1=−1. The bounds B1 and B2 are the edges of the histogram for D1=0. The bound B3 is the edge of the histogram for D1=+1. The bound pairs B0,B1 and B2,B3 can be referred to as opposing histogram bounds, or bound estimates. Each of these bounds can be estimated as explained in the following.
Consider B the current estimate of the bound. If there is any occurrence DR in the particular histogram whose bounds are being estimated, perform the following update:
if DR>B−D then B=B+U
else if DR>B−2·D then B=B−U
else nothing
where DR is the digital residue at the current time, and D and U are programmable parameters. D represents the size of the observation window, and U represents the size of the update step.
For example to estimate B0 the update is performed as follows:
if DR>B0−D then B0=B0+U
else if DR>B0−2·D then B0=B0−U
else nothing
Lower bounds such as B1 and B3 are processed in a very similar manner, except that the histogram is flipped horizontally before the update. In other words, the sign of DR is changed before the update.
A simple graphical description of the method above can be seen in FIG. 9. FIG. 9 can be described as a close-up view of the top histogram of FIG. 8, to better see a particular area of the histogram. In the first graph in FIG. 9 one can see that the bound estimate is too low, therefore the condition DR>B−D will happen more often than the condition {not(DR>B−D) and DR>B−2·D}, hence the bound estimate will tend to move to the right in steps of size U.
In the second graph in FIG. 9 one can see that the bound estimate is correct therefore the condition DR>B−D will happen as often as the condition {not(DR>B−D) and DR>B−2·D}, hence the bound estimate will tend to stay where it is.
Finally, in the third graph in FIG. 9 one can see that the bound estimate is too high therefore the condition DR>B−D will happen less often than the condition {not(DR>B−D) and DR>B−2·D}, hence the bound estimate will tend to move to the left in steps of size U.
There are two problems with the above-described approach, namely the presence of lock-up conditions and the long time required for locking. To see how lock-up conditions can occur, consider the case when B accidentally becomes larger than any possible value of DR. In that case neither of the conditions (DR>B−D and DR>B−2·D) will ever be true, therefore B will never change from its wrong value.
Regarding the second problem, with this algorithm there is a trade-off between the variation in the bound estimate (B) after locking and locking speed. The smaller the update step (U), the smaller the variation in the bound estimate (B) after locking, but also the longer the locking time. Conversely, the larger the update step (U), the larger the variation in the bound estimate (B) after locking, but also the shorter the locking time.
This is important because in practice both short locking times and small variation in the correction factors are desired at the same time. Since the correction factors are calculated from the bound estimates, any variation in the bound estimates will show up as variation in the correction factors.
It is, therefore, desirable to provide an improved calibration technique for pipelined A/D converters that does not suffer from lock-up conditions from which it cannot recover.